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this is information on a product in full production. september 2012 doc id 13264 rev 11 1/45 1 m95m01-df m95m01-r 1-mbit serial spi bus eeprom datasheet ? production data features compatible with the seri al peripheral interface (spi) bus memory array ? 1 mb (128 kbytes) of eeprom ? page size: 256 bytes write ? byte write within 5 ms ? page write within 5 ms additional write lockable page (identification page) write protect: quarter, half or whole memory array high-speed clock: 16 mhz single supply voltage: ? 1.8 v to 5.5 v for m95m01-r ? 1.7 v to 5.5 v for m95m01-df operating temperature range: from -40c up to +85c enhanced esd protection more than 4 million write cycles more than 200-year data retention packages ? rohs compliant and halogen-free (ecopack ? ) so8 (mn) 150 mil width tssop8 (dw) 169 mil width wlcsp (cs) (preliminary data) www.st.com
contents m95m01-df m95m01-r 2/45 doc id 13264 rev 11 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1 serial data output (q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.2 serial data input (d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.3 serial clock (c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.4 chip select (s ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.5 hold (hold ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.6 write protect (w ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.7 v cc supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.8 v ss ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4 connecting to the spi bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.1 spi modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5 operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.1 supply voltage (v cc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.1.1 operating supply voltage v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.1.2 device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.1.3 power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.1.4 power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.2 active power and standby power modes . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.3 hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.4 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.5 data protection and protocol control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6 instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.1 write enable (wren) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.2 write disable (wrdi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.3 read status register (rdsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.3.1 wip bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
m95m01-df m95m01-r contents doc id 13264 rev 11 3/45 6.3.2 wel bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.3.3 bp1, bp0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.3.4 srwd bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.4 write status register (wrsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.5 read from memory array (read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.6 write to memory array (write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.6.1 cycling with error correction code (ecc) . . . . . . . . . . . . . . . . . . . . . . 25 6.7 read identification page (available only in m95m01-d devices) . . . . . . . 26 6.8 write identification page (available only in m95m01-d devices) . . . . . . . 27 6.9 read lock status (available only in m95m01-ddevices) . . . . . . . . . . . . . 28 6.10 lock id (available only in m95m01-d devices) . . . . . . . . . . . . . . . . . . . . . 29 7 power-up and delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.1 power-up state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.2 initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 10 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 11 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 12 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
list of tables m95m01-df m95m01-r 4/45 doc id 13264 rev 11 list of tables table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 2. write-protected block size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 3. instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 4. m95m01-d instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 5. status register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 6. protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 7. address range bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 8. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 9. operating conditions (m95m01-r, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 10. operating conditions (m95m01-df, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 11. ac measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 12. capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 13. cycling performance by groups of four bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 14. memory cell data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 15. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 16. ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 17. so8n ? 8-lead plastic small outline, 150 mils body width, mechanical data . . . . . . . . . . . 38 table 18. tssop8 ? 8-lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 39 table 19. m95m01-dfcs6tp/k, wlcsp 8-bump wafer-level chip scale package mechanical data 41 table 20. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 21. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
m95m01-df m95m01-r list of figures doc id 13264 rev 11 5/45 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. 8-pin package connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. wlcsp connections for m95m01-dfcs6tp/k (top view, marking side, with balls on the underside) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 4. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 5. bus master and memory devices on the spi bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 6. spi modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 7. hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 8. write enable (wren) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7 figure 9. write disable (wrdi) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 10. read status register (rdsr) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 11. write status register (wrsr) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 12. read from memory array (read) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 13. byte write (write) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 14. page write (write) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 15. read identification page sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 16. write identification page sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 17. read lock status sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 18. lock id sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 19. ac measurement i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 20. serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 21. hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 22. serial output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 23. so8n ? 8-lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 38 figure 24. tssop8 ? 8-lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 39 figure 25. m95m01-dfcs6tp/k, wlcsp 8-bump wafer-level chip scale package outline . . . . . . . . 40
description m95m01-df m95m01-r 6/45 doc id 13264 rev 11 1 description the m95m01 devices are electrically eras able programmable memories (eeproms) organized as 131072 x 8 bits, accessed through the spi bus. the m95m01-r devices can operate with a supply range from 1.8 v up to 5.5 v, the m95m01-df devices can operate with a supply range from 1.7 v up to 5.5 v. these devices are guaranteed over the -40 c/+85 c temperature range. the m95m01-df offers an additional page, named the identification page (256 bytes). the identification page can be used to store sensitive application parameters which can be (later) permanently locked in read-only mode. figure 1. logic diagram the spi bus signals are c, d and q, as shown in figure 1 and ta b l e 1 . the device is selected when chip select (s ) is driven low. communications with the device can be interrupted when the hold is driven low. table 1. signal names signal name function direction c serial clock input d serial data input input q serial data output output s chip select input w write protect input hold hold input v cc supply voltage v ss ground ai01789c s v cc m95xxx hold v ss w q c d
m95m01-df m95m01-r description doc id 13264 rev 11 7/45 figure 2. 8-pin package connections (top view) 1. see section 10: package mechanical data section for package dimensions, and how to identify pin 1. figure 3. wlcsp connections for m95m01-dfcs6tp/k (top view, marking side, with balls on the underside) caution: as eeprom cells lose their charge (and so their binary value) when exposed to ultra violet (uv) light, eeprom dice delivered in wafer form or in wlcsp package by stmicroelectronics must never be exposed to uv light. d v ss c hold q sv cc w ai01790d m95xxx 1 2 3 4 8 7 6 5 ms19789v3 v cc d v ss s w hold q c
memory organization m95m01-df m95m01-r 8/45 doc id 13264 rev 11 2 memory organization the memory is organized as shown in the following figure. figure 4. block diagram ms19733v1 hold s w control logic high voltage generator i/o shift register address register and counter data register 1 page x decoder y decoder c d q size of the read only eeprom area status register identification page 1/4 1/2
m95m01-df m95m01-r signal description doc id 13264 rev 11 9/45 3 signal description during all operations, v cc must be held stable and within the specified valid range: v cc (min) to v cc (max). all of the input and output signals must be held high or low (according to voltages of v ih , v oh , v il or v ol , as specified in section 9: dc and ac parameters ). these signals are described next. 3.1 serial data output (q) this output signal is used to transfer data serially out of the device. data is shifted out on the falling edge of serial clock (c). 3.2 serial data input (d) this input signal is used to transfer data serially into the device. it receives instructions, addresses, and the data to be written. values are latched on the rising edge of serial clock (c). 3.3 serial clock (c) this input signal provides the timing of the serial interface. instructions, addresses, or data present at serial data input (d) are latched on the rising edge of serial clock (c). data on serial data output (q) change from the falling edge of serial clock (c). 3.4 chip select (s ) when this input signal is high, the device is de selected and serial data output (q) is at high impedance. the device is in the standby power mode, unless an internal write cycle is in progress. driving chip select (s ) low selects the device, placing it in the active power mode. after power-up, a falling edge on chip select (s ) is required prior to the start of any instruction. 3.5 hold (hold ) the hold (hold ) signal is used to pause any serial communications with the device without deselecting the device. during the hold conditio n, the serial data output (q) is high impedance, and serial data input (d) and serial clock (c) are don?t care. to start the hold condition, the device must be selected, with chip select (s ) driven low.
signal description m95m01-df m95m01-r 10/45 doc id 13264 rev 11 3.6 write protect (w ) the main purpose of this input signal is to freeze the size of the area of memory that is protected against write instructions (as specified by the values in the bp1 and bp0 bits of the status register). this pin must be driven either high or low, and must be stable during all write instructions. 3.7 v cc supply voltage v cc is the supply voltage. 3.8 v ss ground v ss is the reference for all signals, including the v cc supply voltage.
m95m01-df m95m01-r connecting to the spi bus doc id 13264 rev 11 11/45 4 connecting to the spi bus all instructions, addresses and input data bytes are shifted in to the device, most significant bit first. the serial data input (d) is sampled on the first rising edge of the serial clock (c) after chip select (s ) goes low. all output data bytes are shifted out of the device, most significant bit first. the serial data output (q) is latched on the first falling edge of the serial clock (c) after the instruction (such as the read from memory array and read status register instructions) have been clocked into the device. figure 5. bus master and memory devices on the spi bus 1. the write protect (w ) and hold (hold ) signals should be driven, high or low as appropriate. figure 5 shows an example of three memory devices connected to an spi bus master. only one memory device is selected at a time, so only one memory device drives the serial data output (q) line at a time. the other memory devices are high impedance. the pull-up resistor r (represented in figure 5 ) ensures that a device is not selected if the bus master leaves the s line in the high impedance state. in applications where the bus master may leave all spi bus lines in high impedance at the same time (for example, if the bus master is reset during the transmission of an instruction), the clock line (c) must be connected to an external pull-down resistor so that, if all inputs/outputs become high impedance, the c line is pulled low (while the s line is pulled high): this ensures that s and c do not become high at the same time, and so, that the t shch requirement is met. the typical value of r is 100 k .. ai12836b spi bus master spi memory device sdo sdi sck cqd s spi memory device cqd s spi memory device cqd s cs3 cs2 cs1 spi interface with (cpol, cpha) = (0, 0) or (1, 1) w hold w hold w hold rr r v cc v cc v cc v cc v ss v ss v ss v ss r
connecting to the spi bus m95m01-df m95m01-r 12/45 doc id 13264 rev 11 4.1 spi modes these devices can be driven by a microcontroller with its spi peripheral running in either of the following two modes: cpol=0, cpha=0 cpol=1, cpha=1 for these two modes, input data is latched in on the rising edge of serial clock (c), and output data is available from th e falling edge of serial clock (c). the difference between the two modes, as shown in figure 6 , is the clock polarity when the bus master is in stand-by mode and not transferring data: c remains at 0 for (cpol=0, cpha=0) c remains at 1 for (cpol=1, cpha=1) figure 6. spi modes supported ai01438b c msb cpha d 0 1 cpol 0 1 q c msb
m95m01-df m95m01-r operating features doc id 13264 rev 11 13/45 5 operating features 5.1 supply voltage (v cc ) 5.1.1 operating supply voltage v cc prior to selecting the memory and issuing instructions to it, a valid and stable v cc voltage within the specified [v cc (min), v cc (max)] range must be applied (see operating conditions in section 9: dc and ac parameters ). this voltage must remain stable and valid until the end of the transmission of the instruction and, for a write instruction, until the completion of the internal write cycle (t w ). in order to secure a stable dc supply voltage, it is recommended to decouple the v cc line with a suitable capacitor (usually of the order of 10 nf to 100 nf) close to the v cc /v ss device pins. 5.1.2 device reset in order to prevent erroneous instruction decoding and inadvertent write operations during power-up, a power-on-reset (por) circuit is included. at power-up, the device does not respond to any instruction until vcc reaches the por threshold voltage. this threshold is lower than the minimum v cc operating voltage (see operating conditions in section 9: dc and ac parameters ). at power-up, when v cc passes over the por threshold, the device is reset and is in the following state: in standby power mode, deselected, status register values: ? the write enable latch (wel) bit is reset to 0. ? the write in progress (wip) bit is reset to 0. ? the srwd, bp1 and bp0 bits remain unchanged (non-volatile bits). it is important to note that the device must not be accessed until v cc reaches a valid and stable level within the specified [v cc (min), v cc (max)] range, as defined under operating conditions in section 9: dc and ac parameters . 5.1.3 power-up conditions when the power supply is turned on, v cc rises continuously from v ss to v cc . during this time, the chip select (s ) line is not allowed to float but should follow the v cc voltage. it is therefore recommended to connect the s line to v cc via a suitable pull-up resistor (see figure 5 ). in addition, the chip select (s ) input offers a built-in safety feature, as the s input is edge- sensitive as well as level-sensitive: after power-up, the device does not become selected until a falling edge has first been detected on chip select (s ). this ensures th at chip select (s ) must have been high, prior to going low to start the first operation. the v cc voltage has to rise continuously from 0 v up to the minimum v cc operating voltage defined under operating conditions in section 9: dc and ac parameters , and the rise time must not vary faster than 1 v/s.
operating features m95m01-df m95m01-r 14/45 doc id 13264 rev 11 5.1.4 power-down during power-down (continuous decrease of the v cc supply voltage below the minimum v cc operating voltage defined under operating conditions in section 9: dc and ac parameters ), the device must be: deselected (chip select s should be allowed to fo llow the voltage applied on v cc ), in standby power mode (there should not be any internal write cycle in progress). 5.2 active power and standby power modes when chip select (s ) is low, the device is selected, and in the active power mode. the device consumes i cc . when chip select (s ) is high, the device is deselected. if a write cycle is not currently in progress, the device then goes into the standby power mode, and the device consumption drops to i cc1 , as specified in dc characteristics (see section 9: dc and ac parameters ). 5.3 hold condition the hold (hold ) signal is used to pause any serial communications with the device without resetting the clocking sequence. to enter the hold condition, the device must be selected, with chip select (s ) low. during the hold condition, the serial data output (q) is high impedance, and the serial data input (d) and the serial clock (c) are don?t care. normally, the device is kept selected for the whole duration of the hold condition. deselecting the device while it is in the hold condition has the effect of resetting the state of the device, and this mechanism can be used if required to reset any processes that had been in progress. (a)(b) figure 7. hold condition activation the hold condition starts when the hold (hold) signal is driven low when serial clock (c) is already low (as shown in figure 7 ). a. this resets the internal logic, except the wel and wip bits of the status register. b. in the specific case where the device has shifted in a write command (inst + address + data bytes, each data byte being exactly 8 bits), deselec ting the device also triggers the wr ite cycle of this decoded command. ai02029e c hold hold condition hold condition
m95m01-df m95m01-r operating features doc id 13264 rev 11 15/45 the hold condition ends when the hold (hold) signal is driven high when serial clock (c) is already low. figure 7 also shows what happens if the rising and falling edges are not timed to coincide with serial clock (c) being low. 5.4 status register the status register contains a number of status and control bits that can be read or set (as appropriate) by specific instructions. see section 6.3: read stat us register (rdsr) for a detailed description of the status register bits. 5.5 data protection and protocol control the device features the following data protection mechanisms: before accepting the execution of the write and write status register instructions, the device checks whether the number of clock pulses comprised in the instructions is a multiple of eight. all instructions that modify data must be preceded by a write enable (wren) instruction to set the write enable latch (wel) bit. the block protect (bp1, bp0) bits in the status register are used to configure part of the memory as read-only. the write protect (w ) signal is used to protect the block protect (bp1, bp0) bits in the status register. for any instruction to be accepted, and executed, chip select (s ) must be driven high after the rising edge of serial clock (c) for the last bit of the instruction, and before the next rising edge of serial clock (c). two points should be noted in the previous sentence: the ?last bit of the instruction? can be the eighth bit of the instruction code, or the eighth bit of a data byte, depending on the instruction (except for read status register (rdsr) and read (read) instructions). the ?next rising edge of serial clock (c)? might (or might not) be the next bus transaction for some other device on the spi bus. table 2. write-protected block size status register bits protected block protected array addresses bp1 bp0 0 0 none none 0 1 upper quarter 1.80.00h - 1.ff.ffh 1 0 upper half 1.00.00h - 1.ff.ffh 1 1 whole memory 0.00.00h - 1.ff.ffh
instructions m95m01-df m95m01-r 16/45 doc id 13264 rev 11 6 instructions each instruction starts with a si ngle-byte code, as summarized in ta bl e 3 . if an invalid instruction is sent (one not contained in ta b l e 3 ), the device automatically deselects itself. table 3. instruction set instruction descripti on instruction format wren write enable 0000 0110 wrdi write disable 0000 0100 rdsr read status register 0000 0101 wrsr write status register 0000 0001 read read from memory array 0000 0011 write write to memory array 0000 0010 table 4. m95m01-d instruction set instruction description instruction format wren write enable 0000 0110 wrdi write disable 0000 0100 rdsr read status register 0000 0101 wrsr write status register 0000 0001 read read from memory array 0000 0011 write write to memory array 0000 0010 read identification page reads the page dedicated to identification. 1000 0011 (1) 1. address bit a10 must be 0, all other address bits are don't care. write identification page writes the page dedicated to identification. 1000 0010 (1) read lock status reads the lock status of the identificat ion page. 1000 0011 (2) 2. address bit a10 must be 1, all other address bits are don't care. lock id locks the identification page in read-only mode. 1000 0010 (2)
m95m01-df m95m01-r instructions doc id 13264 rev 11 17/45 6.1 write enable (wren) the write enable latch (wel) bit must be set prior to each write and wrsr instruction. the only way to do this is to send a write enable instruction to the device. as shown in figure 8 , to send this instruction to the device, chip select (s ) is driven low, and the bits of the instruction byte are shifted in, on serial data input (d). the device then enters a wait state. it waits for the device to be deselected, by chip select (s ) being driven high. figure 8. write enable (wren) sequence c d ai02281e s q 2 1 34567 high impedance 0 instruction
instructions m95m01-df m95m01-r 18/45 doc id 13264 rev 11 6.2 write disable (wrdi) one way of resetting the write enable latch (wel) bit is to send a write disable instruction to the device. as shown in figure 9 , to send this instruction to the device, chip select (s ) is driven low, and the bits of the instruction byte are shifted in, on serial data input (d). the device then enters a wait state. it waits for a the device to be dese lected, by chip select (s ) being driven high. the write enable latch (wel) bit, in fact, becomes reset by any of the following events: power-up wrdi instruction execution wrsr instruction completion write instruction completion. figure 9. write disable (wrdi) sequence c d ai03750d s q 2 1 34567 high impedance 0 instruction
m95m01-df m95m01-r instructions doc id 13264 rev 11 19/45 6.3 read status register (rdsr) the read status register (rdsr) instruction is used to read the status register. the status register may be read at any time, even while a write or write status register cycle is in progress. when one of these cycles is in progress, it is recommended to check the write in progress (wip) bit before sending a new instruction to the device. it is also possible to read the status register continuously, as shown in figure 10 . figure 10. read status register (rdsr) sequence the status and control bits of the status register are as follows: 6.3.1 wip bit the write in progress (wip) bit indicates whet her the memory is busy with a write or write status register cycle. when set to 1, such a cycle is in progress, when reset to 0, no such cycle is in progress. 6.3.2 wel bit the write enable latch (wel) bit indicates the status of the internal write enable latch. when set to 1, the internal write enable latch is set. when set to 0, the internal write enable latch is reset, and no write or write status register instruction is accepted. the wel bit is returned to its reset state by the following events: power-up write disable (wrdi) instruction completion write status register (wrsr) instruction completion write (write) instruction completion 6.3.3 bp1, bp0 bits the block protect (bp1, bp0) bits are non volatile. they define the size of the area to be software-protected against write instructions. these bits are written with the write status register (wrsr) instruction. when one or both of the block protect (bp1, bp0) bits is set to 1, the relevant memory area (as defined in ta b l e 2 ) becomes protected against write (write) instructions. the block protect (bp1, bp0) bits can be written provided that the hardware protected mode has not been set. c d s 2 1 3456789101112131415 instruction 0 ai02031e q 7 6543210 status register out high impedance msb 7 6543210 status register out msb 7
instructions m95m01-df m95m01-r 20/45 doc id 13264 rev 11 6.3.4 srwd bit the status register write disable (srwd) bit is operated in conjunction with the write protect (w ) signal. the status register write disable (srwd) bit and write protect (w ) signal enable the device to be put in the hardware protected mode (when the status register write disable (srwd) bit is set to 1, and write protect (w ) is driven low). in this mode, the non-volatile bits of the status register (srwd, bp1, bp0) become read-only bits and the write status register (wrsr) instruction is no longer accepted for execution. 6.4 write status register (wrsr) the write status register (wrsr) instruction is used to write new values to the status register. before it can be accepted, a write enable (wren) instruction must have been previously executed. the write status register (wrsr) instruct ion is entered by driving chip select (s ) low, followed by the instruction code, the data byte on serial data input (d) and chip select (s ) driven high. chip select (s ) must be driven high after the rising edge of serial clock (c) that latches in the eighth bit of the data byte, and before the next rising edge of serial clock (c). otherwise, the write status register (wrsr) instruction is not executed. the instruction sequence is shown in figure 11 . figure 11. write status register (wrsr) sequence table 5. status register format b7 b0 srwd 0 0 0 bp1 bp0 wel wip status register write protect block protect bits write enable latch bit write in progress bit c d ai02282d s q 2 1 3456789101112131415 high impedance instruction status register in 0 765432 0 1 msb
m95m01-df m95m01-r instructions doc id 13264 rev 11 21/45 driving the chip select (s ) signal high at a byte boundary of the input data triggers the self- timed write cycle that takes t w to complete (as specified in ac tables under section 9: dc and ac parameters ). while the write status register cycle is in progress, the status register may still be read to check the value of the write in progress (wip) bit: the wip bit is 1 during the self-timed write cycle t w , and 0 when the write cycle is complete. the wel bit (write enable latch) is also reset at the end of the write cycle t w . the write status register (wrsr) instruction enables the user to change the values of the bp1, bp0 and srwd bits: the block protect (bp1, bp0) bits define the size of the area that is to be treated as read-only, as defined in ta bl e 2 . the srwd (status register write disable) bit, in accordance with the signal read on the write protect pin (w ), enables the user to set or reset the write protection mode of the status register itself, as defined in ta b l e 6 . when in write-protected mode, the write status register (wrsr) instruction is not executed. the contents of the srwd and bp1, bp0 bits are updated after the completion of the wrsr instruction, including the t w write cycle. the write status register (wrsr) instruction has no effect on the b6, b5, b4, b1, b0 bits in the status register. bits b6, b5, b4 are always read as 0. the protection features of the device are summarized in ta bl e 6 . when the status register write disable (srwd) bit in the status register is 0 (its initial delivery state), it is possible to write to the status register (provided that the wel bit has previously been set by a wren instruction), regardless of the logic level applied on the write protect (w ) input pin. table 6. protection modes w signal srwd bit mode write protection of the status register memory content protected area (1) 1. as defined by the values in the block protec t (bp1, bp0) bits of the status register. see table 2 . unprotected area (1) 10 software- protected (spm) status register is writable (if the wren instruction has set the wel bit). the values in the bp1 and bp0 bits can be changed. write-protected ready to accept write instructions 00 11 01 hardware- protected (hpm) status register is hardware write- protected. the values in the bp1 and bp0 bits cannot be changed. write-protected ready to accept write instructions
instructions m95m01-df m95m01-r 22/45 doc id 13264 rev 11 when the status register write disable (srwd) bit in the status register is set to 1, two cases should be considered, depending on the state of the write protect (w ) input pin: if write protect (w ) is driven high, it is possible to write to the status register (provided that the wel bit has previously been set by a wren instruction). if write protect (w ) is driven low, it is not possible to write to the status register even if the wel bit has previously been set by a wren instruction. (attempts to write to the status register are rejected, and are not ac cepted for execution). as a consequence, all the data bytes in the memory area, which are software-protected (spm) by the block protect (bp1, bp0) bits in the status register, are also hardware-protected against data modification. regardless of the order of the two events, the hardware-protected mode (hpm) can be entered by: either setting the srwd bit after driving the write protect (w ) input pin low, or driving the write protect (w ) input pin low after setting the srwd bit. once the hardware-protected mode (hpm) has been entered, the only way of exiting it is to pull high the write protect (w ) input pin. if the write protect (w ) input pin is permanently tied high, the hardware-protected mode (hpm) can never be activated, and only the software-protected mode (spm), using the block protect (bp1, bp0) bits in the status register, can be used. 6.5 read from memory array (read) as shown in figure 12 , to send this instruction to the device, chip select (s ) is first driven low. the bits of the instruction byte and address bytes are then shifted in, on serial data input (d). the address is loaded into an internal address register, and the byte of data at that address is shifted out, on serial data output (q). if chip select (s ) continues to be driven low, the internal address register is incremented automatically, and the byte of data at the new address is shifted out. figure 12. read from memory array (read) sequence c d ai13878 s q 23 2 1 345678910 2829303132333435 2221 3210 36 37 38 76543 1 7 0 high impedance data out 1 instruction 24-bit address 0 msb msb 2 39 data out 2
m95m01-df m95m01-r instructions doc id 13264 rev 11 23/45 when the highest address is reached, the addr ess counter rolls over to zero, allowing the read cycle to be continued indefinitely. the whole memory can, therefore, be read with a single read instruction. the read cycle is terminated by driving chip select (s ) high. the rising edge of the chip select (s ) signal can occur at any time during the cycle. the instruction is not accepted, and is not executed, if a write cycle is currently in progress. 6.6 write to memory array (write) as shown in figure 13 , to send this instruction to the device, chip select (s ) is first driven low. the bits of the instruction byte, address byte, and at least one data byte are then shifted in, on serial data input (d). the instruction is terminated by driving chip select (s ) high at a byte boundary of the input data. the self-timed wr ite cycle, triggered by the chip select (s ) rising edge, continues for a period t w (as specified in ac characteristics in section 9: dc and ac parameters ), at the end of which the write in progress (wip) bit is reset to 0. in the case of figure 13 , chip select (s ) is driven high after the eighth bit of the data byte has been latched in, indicating that the instruction is being used to write a single byte. however, if chip select (s ) continues to be driven low, as shown in figure 14 , the next byte of input data is shifted in, so that more than a single byte, starting from the given address towards the end of the same page, can be written in a single internal write cycle. each time a new data byte is shifted in, the least significant bits of the internal address counter are incremented. if more bytes are sent than will fit up to the end of the page, a condition known as ?roll-over? occurs. in case of roll-over, the bytes exceeding the page size are overwritten from location 0 of the same page. table 7. address range bits address significant bits a16-a0 (1) 1. bits a23 to a17 are don?t care. figure 13. byte write (write) sequence ms30905v1 c d s q 23 2 1 345678910 2829303132333435 2221 3210 36 37 38 high impedance instruction 24-bit address 0 765432 0 1 data byte 39
instructions m95m01-df m95m01-r 24/45 doc id 13264 rev 11 the instruction is not accepted, and is not executed, under the following conditions: if the write enable latch (wel) bit has not been set to 1 (by executing a write enable instruction just before), if a write cycle is already in progress, if the device has not been deselected, by driving high chip select (s ), at a byte boundary (after the eighth bit, b0, of the last data byte that has been latched in), if the addressed page is in the region protected by the block protect (bp1 and bp0) bits. note: the self-timed write cycle t w is internally executed as a sequence of two consecutive events: [erase addressed byte(s)], followed by [program addressed byte(s)]. an erased bit is read as ?0? and a programmed bit is read as ?1?. figure 14. page write (write) sequence ms30906v1 c d s c d s 23 2 1 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 22 21 3210 36 37 38 instruction 24-bit address 0 765432 0 1 data byte 1 39 765432 0 1 data byte 2 765432 0 1 data byte 3 65432 0 1 data byte n
m95m01-df m95m01-r instructions doc id 13264 rev 11 25/45 6.6.1 cycling with er ror correctio n code (ecc) the ecc is an internal logic function which is transparent for the spi communication protocol. the ecc logic is implemented on each group of four eeprom bytes (c) . inside a group, if a single bit out of the four bytes happens to be erroneous during a read operation, the ecc detects this bit and replaces it with the correct value. the read reliability is therefore much improved. even if the ecc function is performed on groups of four bytes, a single byte can be written/cycled independently. in this case, the ecc function also writes/cycles the three other bytes located in the same group (c) . as a consequence, the maximum cycling budget is defined at group level and the cycling can be distributed over the four bytes of the group: the sum of the cycles seen by byte0, byte1, byte2 and byte3 of the same group must remain below the maximum value defined in ta b l e 1 3 . c. a group of four bytes is located at addresses [4 *n, 4*n+1, 4*n+2, 4*n+3], where n is an integer.
instructions m95m01-df m95m01-r 26/45 doc id 13264 rev 11 6.7 read identification page (available only in m95m01-d devices) the identification page (256 bytes) is an additional page which can be written and (later) permanently locked in read-only mode. reading this page is achieved with the read identification page instruction (see ta bl e 4 ). the chip select signal (s ) is first driven low, the bits of the instruction byte and address bytes are then shifted in, on serial data input (d). address bit a10 must be 0, upper address bits are don't care, and the data byte pointed to by the lower address bits [a7:a0] is shifted out on serial data output (q). if chip select (s ) continues to be driven low, the internal address register is automatically incremented, and the byte of data at the new address is shifted out. the number of bytes to read in the id page must not exceed the page boundary, otherwise unexpected data is read (e.g.: when reading the id page from location 90d, the number of bytes should be less than or equal to 166d, as the id page boundary is 256 bytes). the read cycle is terminated by driving chip select (s ) high. the rising edge of the chip select (s ) signal can occur at any time during the cycle. the first byte addressed can be any byte within any page. the instruction is not accepted, and is not executed, if a write cycle is currently in progress. figure 15. read identification page sequence ms30907v1 c d s q 23 2 1 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 22 21 3 2 1 0 36 37 38 76543 1 7 0 high impedance data out 1 instruction 24-bit address 0 msb msb 2 39 data out 2
m95m01-df m95m01-r instructions doc id 13264 rev 11 27/45 6.8 write identification page (available only in m95m01-d devices) the identification page (256 bytes) is an additional page which can be written and (later) permanently locked in read-only mode. writing this page is achieved with the write identification page instruction (see ta b l e 4 ). the chip select signal (s ) is first driven low. the bits of the instruction byte, address bytes, and at least one data byte are then shifted in on serial data input (d). address bit a10 must be 0, upper address bits are don't care, the lower address bits [a7:a0] address bits define the byte address inside the identification page. the instruction sequence is shown in figure 16 . figure 16. write identification page sequence ms30909v1 c d s q 23 2 1 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 22 21 3 2 1 0 36 37 38 high impedance instruction 24-bit address 0 765432 0 1 data byte 39
instructions m95m01-df m95m01-r 28/45 doc id 13264 rev 11 6.9 read lock status (available only in m95m01-ddevices) the read lock status instruction (see ta bl e 4 ) is used to check whether the identification page is locked or not in read-only mode. the read lock status sequence is defined with the chip select (s ) first driven low. the bits of the instruction byte and address bytes are then shifted in on serial data input (d). address bit a10 must be 1, all other address bits are don't care. the lock bit is the lsb (least significant bit) of the byte read on serial data output (q). it is at ?1? when the lock is active and at ?0? when the lock is not active. if chip select (s ) continues to be driven low, the same dat a byte is shifted out. the read cycle is terminated by driv ing chip select (s ) high. the instruction sequence is shown in figure 17 . figure 17. read lock status sequence ms30910v1 c d s q 2 1 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 3210 36 37 38 76543 1 7 0 high impedance data out 1 instruction 24-bit address 0 msb msb 2 39 data out 2 23 22 21
m95m01-df m95m01-r instructions doc id 13264 rev 11 29/45 6.10 lock id (available only in m95m01-d devices) the lock id instruction permanently locks the identification page in read-only mode. before this instruction can be accepted, a write enable (wren) instruction must have been executed. the lock id instruction is is sued by driving chip select (s ) low, sending the instruction code, the address and a data byte on serial data input (d), and driving chip select (s ) high. in the address sent, a10 must be equal to 1, all other address bits are don't care. the data byte sent must be equal to the binary value xxxx xx1x, where x = don't care. chip select (s ) must be driven high after the rising edge of serial clock (c) that latches in the eighth bit of the data byte, and before the next rising edge of serial clock (c). otherwise, the lock id instruction is not executed. driving chip select (s ) high at a byte boundary of the input data triggers the self-timed write cycle whose duration is t w (as specified in ac characteristics in section 9: dc and ac parameters ). the instruction sequence is shown in figure 18 . the instruction is discarded, and is not executed, under the following conditions: if a write cycle is already in progress, if the block protect bits (bp1,bp0) = (1,1), if a rising edge on chip select (s ) happens outside of a byte boundary. figure 18. lock id sequence ms30911v1 c d s q 23 2 1 3 4 5 6 7 8 9 10 2829303132333435 22 21 3 2 1 0 36 37 38 high impedance instruction 24-bit address 0 765432 0 1 data byte 39
power-up and delivery state m95m01-df m95m01-r 30/45 doc id 13264 rev 11 7 power-up and delivery state 7.1 power-up state after power-up, the device is in the following state: standby power mode, deselected (after power-up, a falling edg e is required on chip select (s ) before any instructions can be started), not in the hold condition, the write enable latch (wel) is reset to 0, write in progress (wip) is reset to 0. the srwd, bp1 and bp0 bits of the status register are unchanged from the previous power-down (they are non-volatile bits). 7.2 initial delivery state the device is delivered with the memory array set to all 1s (each byte = ffh). the status register write disable (srwd) and block protec t (bp1 and bp0) bits are initialized to 0.
m95m01-df m95m01-r maximum rating doc id 13264 rev 11 31/45 8 maximum rating stressing the device outside the ratings listed in ta bl e 8 may cause permanent damage to the device. these are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operat ing sections of this specification, is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 8. absolute maximum ratings symbol parameter min. max. unit ambient operating temperature ?40 130 c t stg storage temperature ?65 150 c t lead lead temperature during soldering see note (1) 1. compliant with jedec std j-std-020 (for small body, sn-pb or pb assembly), with the st ecopack? 7191395 specification, and with the european directive on restrictions on hazar dous substances (rohs) 2002/95/eu. c v o output voltage ?0.50 v cc +0.6 v v i input voltage ?0.50 6.5 v v cc supply voltage ?0.50 6.5 v i ol dc output current (q = 0) 5 ma i oh dc output current (q = 1) 5 ma v esd electrostatic discharge voltage (human body model) (2) 2. positive and negative pulses applied on different comb inations of pin connect ions, according to aec- q100-002 (compliant with jedec std jesd22-a114, c1=100 pf, r1=1500 , r2=500 ). 4000 v
dc and ac parameters m95m01-df m95m01-r 32/45 doc id 13264 rev 11 9 dc and ac parameters this section summarizes the operating conditions and the dc/ac characteristics of the device. figure 19. ac measurement i/o waveform table 9. operating conditions (m95m01-r, device grade 6) symbol parameter min. max. unit v cc supply voltage 1.8 5.5 v t a ambient operating temperature ?40 85 c table 10. operating conditions (m95m01-df, device grade 6) symbol parameter min. max. unit v cc supply voltage 1.7 5.5 v t a ambient operating temperature ?40 85 c table 11. ac measurement conditions symbol parameter min. max. unit c l load capacitance 100 pf input rise and fall times ns input pulse voltages 0.2 v cc to 0.8 v cc v input and output timing reference voltages 0.3 v cc to 0.7 v cc v ai00825c 0.8 v cc 0.2 v cc 0.7 v cc 0.3 v cc input and output timing reference levels input voltage levels
m95m01-df m95m01-r dc and ac parameters doc id 13264 rev 11 33/45 table 12. capacitance symbol parameter test conditions (1) 1. sampled only, not 100% tested, at t a = 25 c and a frequency of 5 mhz. min. max. unit c out output capacitance (q) v out = 0 v 8 pf c in input capacitance (d) v in = 0 v 8 pf input capacitance (other pins) v in = 0 v 6 pf table 13. cycling performance by groups of four bytes symbol parameter (1) 1. cycling performance for products identified by process letters kb. test conditions min. max. unit ncycle write cycle endurance (2) 2. the write cycle endurance is defined for groups of four data bytes located at addresses [4*n, 4*n+1, 4*n+2, 4*n+3] where n is an integer. the write cycle endurance is defined by characterization and qualification. ta 25 c, v cc (min) < v cc < v cc (max) 4,000,000 write cycle (3) 3. a write cycle is executed when either a page write, a byte write, a wrsr, a wrid or an lid instruction is decoded. when using the byte write, the page writ e or the wrid instruction, refer also to section 6.6.1: cycling with error correction code (ecc) . ta = 85 c, v cc (min) < v cc < v cc (max) 1,200,000 table 14. memory cell data retention parameter test conditions min. unit data retention (1) 1. for products identified by process letters kb. the data retention behavior is checked in production. the 200-year limit is defined from characterization and qualification results. ta = 55 c 200 year
dc and ac parameters m95m01-df m95m01-r 34/45 doc id 13264 rev 11 table 15. dc characteristics symbol parameter test conditions min max unit i li input leakage current v in = v ss or v cc 2 a i lo output leakage current s = v cc , v out = v ss or v cc 2 a i cc supply current (read) c=0.1v cc /0.9 v cc at 2 mhz, v cc =1.8v (1) , q = open 1.5 ma c=0.1v cc /0.9 v cc at 5 mhz, v cc =1.8v (1) , q = open 2 (2) ma c=0.1v cc /0.9 v cc at 5 mhz, v cc = 2.5 v, q = open 4ma c=0.1v cc /0.9 v cc at 10 mhz, v cc = 2.5 v, q = open 2 (2) c=0.1v cc /0.9 v cc at 5 mhz, v cc = 5 v, q = open 5ma c=0.1v cc /0.9 v cc at 10 mhz, v cc = 5.5 v, q = open 5 (2) i cc0 (3) supply current (write) during t w , s = v cc ,5ma i cc1 supply current (standby power mode) s = v cc , v in = v ss or v cc , v cc = 1.8 v (1) 3a s = v cc , v in = v ss or v cc , v cc = 1.8 v (1) , temp = 25 c (or less) 1a s = v cc , v in = v ss or v cc , v cc = 2.5 v 3a s = v cc , v in = v ss or v cc , v cc = 2.5 v, temp = 25 c (or less) 1a s = v cc , v in = v ss or v cc , v cc = 5.5 v 5a s = v cc , v in = v ss or v cc , v cc = 5.5 v, temp = 25 c (or less) 1.5 a v il input low voltage 1.8 v (1) v cc < 2.5 v ?0.45 0.25 v cc v 2.5 v v cc 5.5 v ?0.45 0.3 v cc v ih input high voltage 1.8 v (1) v cc < 2.5 v 0.75 v cc v cc +1 v 2.5 v v cc 5.5 v 0.7 v cc v cc +1 v ol output low voltage i ol = 0.15 ma, v cc = 1.8 v (1) 0.3 v v cc = 2.5 v, i ol = 1.5 ma or v cc = 5 v, i ol = 2 ma 0.4 v v oh output high voltage i oh = ?0.1 ma, v cc = 1.8 v (1) 0.8 v cc v v cc = 2.5 v, i oh = ?0.4 ma or v cc = 5 v, i oh = ?2 ma 1. or v cc = 1.7 v for the m95m01-df. 2. for devices identified by process letter k. 3. characterized value, not tested in production.
m95m01-df m95m01-r dc and ac parameters doc id 13264 rev 11 35/45 table 16. ac characteristics test conditions specified in table 9 , table 10 and table 11 symbol alt. parameter v cc 1.7 v (1) v cc 1.8 v (2) v cc 2.5 v (3) v cc 4.5 v (1) unit min. max. min. max. min. max. min. max. f c f sck clock frequency d.c. 2 d.c. 5 d.c. 10 d.c. 16 mhz t slch t css1 s active setup time 150 60 30 20 ns t shch t css2 s not active setup time 150 60 30 20 ns t shsl t cs s deselect time 200 60 40 25 ns t chsh t csh s active hold time 150 60 30 20 ns t chsl s not active hold time 150 60 30 20 ns t ch (4) t clh clock high time 200 90 40 25 ns t cl (4) t cll clock low time 200 90 40 25 ns t clch (5) t rc clock rise time 2 2 2 s t chcl (5) t fc clock fall time 2 2 2 s t dvch t dsu data in setup time 50 20 10 10 ns t chdx t dh data in hold time 50 20 10 10 ns t hhch clock low hold time after hold not active 150 60 30 25 ns t hlch clock low hold time after hold active 150 60 30 20 ns t clhl clock low set-up time before hold active 0000ns t clhh clock low set-up time before hold not active 0000ns t shqz (5) t dis output disable time 200 80 40 25 ns t clqv t v clock low to output valid 200 80 40 25 ns t clqx t ho output hold time 0 0 0 0 ns t qlqh (5) t ro output rise time 200 80 40 25 ns t qhql (5) t fo output fall time 200 80 40 25 ns t hhqv t lz hold high to output valid 200 80 40 25 ns t hlqz (5) t hz hold low to output high-z 200 80 40 25 ns t w t wc write time 5555ms 1. for devices identified by process letter k. 2. previous products (identif ied with process letter a) were specified with f c (max) = 2 mhz, with the same ac values as defined in the 1.7 v columns in this table. 3. previous products (identif ied with process letter a) were specified with f c (max) = 5 mhz, with the same ac values as defined in the 1.8 v columns in this table. 4. t ch + t cl must never be less than the shortest possible clock period, 1 / f c (max) 5. value guaranteed by characterization, not 100% tested in production.
dc and ac parameters m95m01-df m95m01-r 36/45 doc id 13264 rev 11 figure 20. serial input timing figure 21. hold timing c d ai01447d s msb in q tdvch high impedance lsb in tslch tchdx tclch tshch tshsl tchsh tchsl tch tcl tchcl c q ai01448c s hold tclhl thlch thhch tclhh thhqv thlqz
m95m01-df m95m01-r dc and ac parameters doc id 13264 rev 11 37/45 figure 22. serial output timing c q ai01449f s d addr lsb in tshqz tch tcl tqlqh tqhql tchcl tclqx tclqv tshsl tclch
package mechanical data m95m01-df m95m01-r 38/45 doc id 13264 rev 11 10 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. figure 23. so8n ? 8-lead plastic small outlin e, 150 mils body width, package outline 1. drawing is not to scale. table 17. so8n ? 8-lead plastic small outline, 150 mils body width, mechanical data symbol millimeters inches (1) 1. values in inches are converted fr om mm and rounded to four decimal digits. typ min max typ min max a 1.750 0.0689 a1 0.100 0.250 0.0039 0.0098 a2 1.250 0.0492 b 0.280 0.480 0.0110 0.0189 c 0.170 0.230 0.0067 0.0091 ccc 0.100 0.0039 d 4.900 4.800 5.000 0.1929 0.1890 0.1969 e 6.000 5.800 6.200 0.2362 0.2283 0.2441 e1 3.900 3.800 4.000 0.1535 0.1496 0.1575 e 1.270 - - 0.0500 - - h 0.250 0.500 0.0098 0.0197 k 08 08 l 0.400 1.270 0.0157 0.0500 l1 1.040 0.0409 so-a e1 8 ccc b e a d c 1 e h x 45? a2 k 0.25 mm l l1 a1 gauge plane
m95m01-df m95m01-r package mechanical data doc id 13264 rev 11 39/45 figure 24. tssop8 ? 8-lead thin shrink small outline, package outline 1. drawing is not to scale. table 18. tssop8 ? 8-lead thin shrink small outline, package mechanical data symbol millimeters inches (1) 1. values in inches are converted fr om mm and rounded to four decimal digits. typ min max typ min max a 1.200 0.0472 a1 0.050 0.150 0.0020 0.0059 a2 1.000 0.800 1.050 0. 0394 0.0315 0.0413 b 0.190 0.300 0.0075 0.0118 c 0.090 0.200 0.0035 0.0079 cp 0.100 0.0039 d 3.000 2.900 3.100 0. 1181 0.1142 0.1220 e 0.650 - - 0.0256 - - e 6.400 6.200 6.600 0. 2520 0.2441 0.2598 e1 4.400 4.300 4.500 0. 1732 0.1693 0.1772 l 0.600 0.450 0.750 0. 0236 0.0177 0.0295 l1 1.000 0.0394 0 8 0 8 n8 8 tssop8am 1 8 cp c l e e1 d a2 a e b 4 5 a1 l1
package mechanical data m95m01-df m95m01-r 40/45 doc id 13264 rev 11 figure 25. m95m01-dfcs6tp/k, wlcsp 8-bump wafer-level chip scale package outline 1. drawing is not to scale. (4x) aaa wafer back side d e side view detail a a2 a e1 e2 e g f bumps side f detail a rotated 90 bump eee a1 seating plane 1ce_me_v1 e3 g b bbb z z x ccc m y ? z ? ddd m x y z z reference orientation
m95m01-df m95m01-r package mechanical data doc id 13264 rev 11 41/45 table 19. m95m01-dfcs6tp/k, wlcsp 8-bump wafer-level chip scale package mechanical data symbol millimeters inches (1) 1. values in inches are converted fr om mm and rounded to four decimal digits. typ min max typ min max a 0.540 0.500 0.580 0.0213 0.0197 0.0228 a1 0.190 0.0075 a2 0.350 0.0138 b 0.270 0.0106 d 2.560 2.580 0.1008 0.1016 e 1.698 1.718 0.0669 0.0676 e 1.000 0.0394 e1 0.866 0.0341 e2 0.500 0.0197 e3 0.500 0.0197 f 0.416 0.0164 g 0.780 0.0307 n (number of terminals) 8 8 aaa 0.110 0.0039 bbb 0.110 0.0039 ccc 0.110 0.0039 ddd 0.060 0.0020 eee 0.060 0.0020
part numbering m95m01-df m95m01-r 42/45 doc id 13264 rev 11 11 part numbering table 20. ordering information scheme example: m95m01 r mn 6 t p /k device type m95 = spi serial access eeprom device function m01- = 1 mbit (131072 x 8) m01-d = 1 mbit plus identification page operating voltage r = v cc = 1.8 to 5.5 v f = v cc = 1.7 to 5.5 v package mn = so8 (150 mil width) dw = tssop8 (169 mil width) cs = wlcsp device grade 6 = industrial temperature range, ?40 to 85 c. device tested with standard test flow option blank = standard packing t = tape and reel packing plating technology p = rohs compliant and halogen-free (ecopack?) process (1) 1. the process letters apply to wlcsp devices only. the process letters appear on the device package (marking) and on the shipment box. pl ease contact your nearest st sales office for further information. /k= manufacturing technology code
m95m01-df m95m01-r revision history doc id 13264 rev 11 43/45 12 revision history table 21. document revision history date revision changes 13-mar-2007 1 initial release. 15-may-2007 2 v cc conditions modified in table 15: ac characteristics (m95m01-r6, v cc <2.5v) . small text changes. 21-jun-2007 3 the device endurance is specified at more than 1 000 000 (1 million) cycles (corrected on page 1 ). 17-jul-2007 4 schmitt trigger inputs for enhanced noise margin added to features on page 1 . v il and v ih values modified according to voltage range in table 12: dc characteristics (m95m01-r6) . 24-jan-2008 5 document status promot ed from preliminary data to full datasheet. i cc0 modified in table 12: dc characteristics (m95m01-r6) . in section 11: package mechanical data , values in inches are converted from mm and rounded to 4 decimal digits. table 20: available products (package, voltage range, temperature grade) added. small text changes. 07-may-2009 6 wlcsp package added (see figure 3: wlcsp connections (bottom view, bump side) and section 11: package mechanical data ). section 3: connecting to the spi bus updated. section 4.1: supply voltage (v cc ) updated. note added to section 6.6: write to memory array (write) . note added to table 15: ac characteristics (m95m01-r6, v cc <2.5v) . figure 16: serial input timing , figure 17: hold timing and figure 18: serial output timing updated. ecopack text updated under section 11: package mechanical data . 30-jul-2009 7 m95m01-w device grade 3 devices added (see table 9: operating conditions (m95m01-w3) , table 13: dc characteristics (m95m01-w3) , table 14: ac characteristics (m95m01-r6 and m95m01-w3, v cc 2.5 v) and table 20: ordering information scheme ). 26-mar-2012 8 added tssop package. updated ? table 12: dc characteristics (m95m01-r6) ? table 13: dc characteristics (m95m01-w3) ? table 14: ac characteristics (m95m01-r6 and m95m01-w3, v cc 2.5 v) ? table 15: ac characteristics (m95m01-r6, v cc <2.5v) ? figure 15: ac measurement i/o waveform ? ?process? in section 12: part numbering deleted: ? table 20: available products (pack age, voltage range, temperature grade)
revision history m95m01-df m95m01-r 44/45 doc id 13264 rev 11 20-jun-2012 9 datasheet split into: ? m95m01-125 datasheet for automotive products (range 3), ? m95m01-df, m95m01-r (this datas heet) for standard products (range 6). updated: ? wlcsp package dimensions: figure 25: m95m 01-dfcs6tp/k, wlcsp 8-bump wafer-level chip scale package outline and table 19: m95m01-dfcs6tp/k, wlcsp 8-bump wafer-level chip scale package mechanical data ? cycling and data retention performances (4 million write cycles, 200- year data retention) ? table 15: dc characteristics updated with 1.7 v values ? table 16: ac characteristics updated with 16 mhz clock added: ? identification page (m95m01-df) ? 1.7 v/5.5 v device (reference m95m01-df) deleted: ? reference m95m01-w3 06-jul-2012 10 updated wlcsp package reference from ?ct? to ?cs?. 3-sep-2012 11 fixed some errors in figure 3: wlcsp connections for m95m01- dfcs6tp/k (top view, marking side, with balls on the underside) table 21. document revision history (continued) date revision changes
m95m01-df m95m01-r doc id 13264 rev 11 45/45 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by two authorized st representatives, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2012 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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